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UCD3138128 데이터시트(PDF) 13 Page - Texas Instruments

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부품명 UCD3138128
상세설명  UCD3138x Highly-Integrated Digital Controller For Isolated Power
PDF  80 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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UCD3138128 데이터시트(HTML) 13 Page - Texas Instruments

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UCD3138128, UCD3138A64
www.ti.com
SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014
Timing Requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
t(HIGH)
Clock high period(3)
35
ms
Cumulative clock low slave extend
t(LOW:SEXT)
25
ms
time(4)
20 + 0.1
tf
Clock/data fall time
Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15)
300
ns
Cb(5)
20 + 0.1
tr
Clock/data rise time
Fall time tf = 0.9 VDD to (VILmax – 0.15)
300
ns
Cb(5)
Cb
Total capacitance of one bus line
400
pF
(3)
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(4)
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(5)
Cb (pF)
Figure 1. IC/SMBUS/PMBUS Timing Diagram2
Figure 2. Bus Timing In Extended Mode
Copyright © 2014, Texas Instruments Incorporated
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