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AR0130CSSC00SPBA0-DP 데이터시트(PDF) 35 Page - ON Semiconductor |
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AR0130CSSC00SPBA0-DP 데이터시트(HTML) 35 Page - ON Semiconductor |
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35 / 53 page ![]() AR0130 DS Rev. L Pub. 6/15 EN 35 ©Semiconductor Components Industries, LLC, 2015. AR0130: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Current Location This sequence (Figure 23) starts in the same way as the single READ from current loca- tion (Figure 21). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 23: Sequential READ, Start from Current Location Single WRITE to Random Location This sequence (Figure 24) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 24: Single WRITE to Random Location Sequential WRITE, Start at Random Location This sequence (Figure 25) starts in the same way as the single WRITE to random location (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 25: Sequential WRITE, Start at Random Location Read Data Read Data Previous Reg Address, N N+1 N+2 N+L-1 N+L Read Data Slave Address A 1 Read Data A P S A A A Slave Address 0 S A Reg Address[15:8] A Reg Address[7:0] A P Previous Reg Address, N Reg Address, M M+1 A A Write Data Slave Address 0 S A Reg Address[15:8] A A Reg Address[7:0] A Previous Reg Address, N Reg Address, M M+1 M+2 M+1 M+3 A A A M+L-2 M+L-1 M+L A A P Write Data Write Data Write Data Write Data Write Data |
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