전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AR0134CSSC00SUEAH-GEVB 데이터시트(PDF) 11 Page - ON Semiconductor

부품명 AR0134CSSC00SUEAH-GEVB
상세설명  Inch 1.2 Mp CMOS Digital Image Sensor with Global Shutter
PDF  41 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AR0134CSSC00SUEAH-GEVB 데이터시트(HTML) 11 Page - ON Semiconductor

Back Button AR0134CSSC00SUEAH-GEVB Datasheet HTML 7Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 8Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 9Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 10Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 11Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 12Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 13Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 14Page - ON Semiconductor AR0134CSSC00SUEAH-GEVB Datasheet HTML 15Page - ON Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 41 page
background image
AR0134_DS Rev. G Pub. 6/15 EN
11
©Semiconductor Components Industries, LLC,2015.
AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Configuration and Pinout
Figure 5:
Typical Configuration: Parallel Pixel Data Interface
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire
speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The serial interface output pads can be left unconnected if the parallel output interface is used.
5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Refer to the AR0134 demo headboard schematics for circuit recom-
mendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that cou-
pling with the digital power planes is minimized.
VDD
Master clock
(6–50 MHz)
SDATA
SCLK
TEST
FLASH
FRAME_VALID
DOUT [11:0]
EXTCLK
DGND
Digital
ground
Analog
ground
Digital
core
power1
To
controller
From
Controller
LINE_VALID
PIXCLK
RESET_BAR
VDD_IO
Digital
I/O
power1
VAA
VAA_PIX
Analog
power1
VDD_PLL
PLL
power1
Analog
power1
VAA_PIX
VDD_IO
VDD_PLL
VDD
VAA
TRIGGER
OE_BAR
STANDBY
AGND



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com