AR0134CSSC00SUEAH-GEVB datasheet(32/41 Pages) ONSEMI

32 / 41 page

AR0134_DS Rev. G Pub. 6/15 EN

©Semiconductor Components Industries, LLC,2015.

AR0134: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

Power-On Reset and Standby Timing

Power-Up Sequence

The recommended power-up sequence for the AR0134 is shown in Figure 19. The avail-

able power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the

separation specified below.

1. Turn on VDD_PLL power supply.

2. After 0–10s, turn on VAA and VAA_PIX power supply.

3. After 0–10s, turn on VDD_IO power supply.

4. After the last power supply is stable, enable EXTCLK.

5. If RESET_BAR is in a LOW state, hold RESET_BAR LOW for at least 1ms.

If RESET_BAR is in a HIGH state, assert RESET_BAR for at least 1ms.

6. Wait 160000 EXTCLKs (for internal initialization into software standby).

7. Configure PLL, output, and image settings to desired values.

8. Wait 1ms for the PLL to lock.

9. Set streaming mode (R0x301a[2] = 1).

Figure 19:

Power Up

Notes:

1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.

2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard

reset is held down by RC circuit, then the RC time must include the all power rail settle time and

Xtal settle time.

Table 18:

Power-Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX

–

s

VAA/VAA_PIX to VDD_IO

–

s

VDD_IO to VDD

–

s

VDD to VDD_SLVS

–

s

Xtal settle time

–

301

–ms

Hard Reset

––

Internal Initialization

160000

–

EXTCLKs

PLL Lock Time

–

VDD_PLL (2.8)

VAA_PIX

VAA (2.8)

VDD_IO (1.8/2.8)

VDD (1.8)

VDD_SLVS (0.4)

EXTCLK

RESET_BAR

Hard Reset

Internal

Initialization

Software

Standby

PLL Lock

Streaming

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