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GD25LQ40 데이터시트(PDF) 16 Page - ELM Electronics |
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GD25LQ40 데이터시트(HTML) 16 Page - ELM Electronics |
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16 / 59 page ![]() 16 Rev.1.0 59 - http://www.elm-tech.com GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash CS# SCLK IO0 IO1 IO2 IO3 0 1 Command 04H Figure 3a. Write Disable Sequence Diagram (QPI) 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z Figure 3. Write Disable Sequence Diagram |
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