Z86L7208FSC datasheet(28/71 Pages) ZILOG

28 / 71 page

Z86C72/C92/L72/L92

IR Microcontroller

Zilog

6-28

P R E L I M I N A R Y

DS97LVO0900

PIN FUNCTIONS (Continued)

/RESET (Input, active Low). Initializes the MCU. Reset is

accomplished either through Power-On, Watch-Dog Tim-

er, Stop-Mode Recovery, Low Voltage detection, or exter-

nal reset. During Power-On Reset and Watch-Dog Timer

Reset, the internally generated reset drives the reset pin

Low for the POR time. Any devices driving the reset line

should be open-drain in order to avoid damage from a pos-

sible conflict during reset conditions. Pull-up is provided in-

ternally. There is no internal condition that will not allow an

external reset to occur.

After the POR time, /RESET is a Schmitt-triggered input.

To avoid asynchronous and noisy reset problems, the

Z86L/CX2 is equipped with a reset filter of four external

clocks (4TpC). If the external reset signal is less than 4TpC

in duration, no reset occurs. On the fifth clock after the re-

set is detected, an internal RST signal is latched and held

for an internal register count of 18 external clocks, or for

the duration of the external reset, whichever is longer.

During the reset cycle, /DS is held active Low while /AS cy-

cles at a rate of TpC/2. Program execution begins at loca-

tion 000CH, 5-10 TpC cycles after the RST is released. For

Power-On Reset, the typical reset output time is 5 ms. The

Z86L/CX2 does not reset WDTMR, SMR, P2M, P2, P3, or

P3M registers on a Stop-Mode Recovery operation.

Figure 15. Port 3 Conﬁguration

Port 3

(I/O or Handshake)

Z86L7X

MCU

Pref1

P31

P32

P33

P34

P35

P36

P37

Note:

P31, 32, 33 have a 200 K

Ω

mask option.

200 K

Ω

Mask

Option

R247 = P3M

P31 (AN1)

P32 (AN2)

P33 (REF2)

From Stop-Mode

Recovery Source of SMR

1 = Analog

0 = Digital

IRQ2, P31 Data Latch

IRQ0, P32 Data Latch

IRQ1, P33 Data Latch

DIG.

AN.

Pref1*

Comp1

Comp2

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