L8708H datasheet(46/66 Pages) ZILOG

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Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

P R E L I M I N A R Y

DS96LV00800

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder controlled by

the Interrupt Priority register. An interrupt machine cycle is

activated when an interrupt request is granted. This dis-

ables all subsequent interrupts, saves the Program

Counter and Status Flags, and then branches to the pro-

gram memory vector location reserved for that interrupt.

All Z86LXX interrupts are vectored through locations in the

program memory. This memory location and the next byte

contain the 16-bit address of the interrupt service routine

for that particular interrupt request. To accommodate

polled interrupt systems, interrupt inputs are masked and

the Interrupt Request register is polled to determine which

of the interrupt requests need service.

An interrupt resulting from AN1 is mapped into IRQ2, and

an interrupt from AN2 is mapped into IRQ0. Interrupts

IRQ2 and IRQ0 may be rising, falling, or both edge trig-

gered, and are programmable by the user. The software

can poll to identify the state of the pin.

Programming bits for the Interrupt Edge Select are located

in the IRQ Register (R250), bits D7 and D6 . The configu-

ration is shown in Table 6.

Clock. The Z86LXX on-chip oscillator has a high-gain,

parallel-resonant amplifier for connection to a crystal, LC,

ceramic resonator, or any suitable external clock source

(XTAL1 = Input, XTAL2 = Output). The crystal should be

AT cut, 1 MHz to 8 MHz maximum, with a series resistance

(RS) less than or equal to 100 Ohms. The Z86LXX on-chip

oscillator may be driven with a low cost RC network or oth-

er suitable external clock source.

For 32 kHz crystal operation, an external feedback resistor

(Rf) and a serial resistor (Rd) are required. See Figure 37.

The crystal should be connected across XTAL1 and

XTAL2 using the recommended capacitors (capacitance

greater than or equal to 22 pF) from each pin to ground.

The RC oscillator configuration is an external resistor con-

nected from XTAL1 to XTAL2, with a frequency-setting ca-

pacitor from XTAL1 to ground (Figure 37).

Table 5. Interrupt Types, Sources, and Vectors

Name

Source

Vector

Location

Comments

IRQ0

/DAV0,

IRQ0

0, 1

External

(P32), Rising

Falling Edge

Triggered

IRQ1,

IRQ1

2, 3

External

(P33), Falling

Edge Triggered

IRQ2

/DAV2,

IRQ2, TIN

4, 5

External

(P31), Rising

Falling Edge

Triggered

IRQ3

T16

6, 7

Internal

IRQ4

8, 9

Internal

Table 6. IRQ Register

IRQ

Interrupt Edge

IRQ2(P31)

IRQ0 (P32)

R/F

Notes:

F = Falling Edge

R = Rising Edge

In analog mode, the Stop-Mode Recovery sources selected by

the SMR register are connected to the IRQ1 input. Any of the

Stop-Mode Recovery sources for SMR (except P31, P32, and

P33) can be used to generate IRQ1 (falling edge triggered).

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