UPSD3312D datasheet(52/272 Pages) STMICROELECTRONICS

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UPSD33xx instruction set summary

UPSD33xx

52/272

Doc ID 9685 Rev 7

XRL

A, @Ri

Exclusive-OR indirect SRAM

to ACC

1 byte/1 cycle

XRL

A, #data

Exclusive-OR immediate data

to ACC

2 byte/1 cycle

XRL

direct, A

Exclusive-OR ACC to direct

byte

2 byte/1 cycle

XRL

direct, #data

Exclusive-OR immediate data

to direct byte

3 byte/2 cycle

CLR

Clear ACC

1 byte/1 cycle

CPL

Compliment ACC

1 byte/1 cycle

Rotate ACC left

1 byte/1 cycle

RLC

Rotate ACC left through the

carry

1 byte/1 cycle

Rotate ACC right

1 byte/1 cycle

RRC

Rotate ACC right through the

carry

1 byte/1 cycle

All mnemonics copyrighted ©Intel Corporation 1980.

Table 8.

Data transfer instruction set

Mnemonic(1)

and use

Description

Length/cycles

MOV

A, Rn

Move register to ACC

1 byte/1 cycle

MOV

A, direct

Move direct byte to ACC

2 byte/1 cycle

MOV

A, @Ri

Move indirect SRAM to ACC

1 byte/1 cycle

MOV

A, #data

Move immediate data to ACC

2 byte/1 cycle

MOV

Rn, A

Move ACC to register

1 byte/1 cycle

MOV

Rn, direct

Move direct byte to register

2 byte/2 cycle

MOV

Rn, #data

Move immediate data to

2 byte/1 cycle

MOV

direct, A

Move ACC to direct byte

2 byte/1 cycle

MOV

direct, Rn

Move register to direct byte

2 byte/2 cycle

MOV

direct, direct

Move direct byte to direct

3 byte/2 cycle

MOV

direct, @Ri

Move indirect SRAM to direct

byte

2 byte/2 cycle

MOV

direct, #data

Move immediate data to

direct byte

3 byte/2 cycle

MOV

@Ri, A

Move ACC to indirect SRAM

1 byte/1 cycle

Table 7.

Logical instruction set (continued)

Mnemonic(1)

and use

Description

Length/cycles

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