UPSD3312D datasheet(80/272 Pages) STMICROELECTRONICS

80 / 272 page

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I/O ports of MCU module

UPSD33xx

80/272

Doc ID 9685 Rev 7

Figure 18.

MCU I/O cell block diagram for Port 4

Table 33.

P1: I/O Port 1 register (SFR 90h, reset value FFh)

Table 34.

P1 register bit definition

P4.X Pin

Digital_Pin_Data_In

PRE

SFR

P4.X

Latch

8032 Data Bus Bit

GPIO P4.X SFR

Write Latch

MCU_Reset

P4.X SFR Read Latch

(for R-M-W instructions)

P4.X SFR Read Pin

Select_Alternate_Func

For PCA Alternate Function

IN 1

IN 0

MUX

VCC

SEL

Enable_Push_Pull

WEAK

PULL-UP, B

STONGER

PULL-UP, A

LOW

SIDE

HIGH

SIDE

DELAY,

1 MCU_CLK

DELAY,

1 MCU_CLK

Digital_Alt_Func_Data_Out

AI09602

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Bit

Symbol

R/W

Function(1)

Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by

firmware or by a reset event.

7P1.7

R,W

Port pin 1.7

6P1.6

R,W

Port pin 1.6

5P1.5

R,W

Port pin 1.5

4P1.4

R,W

Port pin 1.4

3P1.3

R,W

Port pin 1.3

2P1.2

R,W

Port pin 1.2

1P1.1

R,W

Port pin 1.1

0P1.0

R,W

Port pin 1.0

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