UPSD3312D datasheet(51/272 Pages) STMICROELECTRONICS

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UPSD33xx

UPSD33xx instruction set summary

Doc ID 9685 Rev 7

51/272

INC

Increment register

1 byte/1 cycle

INC

direct

Increment direct byte

2 byte/1 cycle

INC

@Ri

Increment indirect SRAM

1 byte/1 cycle

DEC

Decrement ACC

1 byte/1 cycle

DEC

Decrement register

1 byte/1 cycle

DEC

direct

Decrement direct byte

2 byte/1 cycle

DEC

@Ri

Decrement indirect SRAM

1 byte/1 cycle

INC

DPTR

Increment Data Pointer

1 byte/2 cycle

MUL

Multiply ACC and B

1 byte/4 cycle

DIV

Divide ACC by B

1 byte/4 cycle

Decimal adjust ACC

1 byte/1 cycle

All mnemonics copyrighted ©Intel Corporation 1980.

Table 7.

Logical instruction set

Mnemonic(1)

and use

Description

Length/cycles

ANL

A, Rn

AND register to ACC

1 byte/1 cycle

ANL

A, direct

AND direct byte to ACC

2 byte/1 cycle

ANL

A, @Ri

AND indirect SRAM to ACC

1 byte/1 cycle

ANL

A, #data

AND immediate data to ACC

2 byte/1 cycle

ANL

direct, A

AND ACC to direct byte

2 byte/1 cycle

ANL

direct, #data

AND immediate data to direct

byte

3 byte/2 cycle

ORL

A, Rn

OR register to ACC

1 byte/1 cycle

ORL

A, direct

OR direct byte to ACC

2 byte/1 cycle

ORL

A, @Ri

OR indirect SRAM to ACC

1 byte/1 cycle

ORL

A, #data

OR immediate data to ACC

2 byte/1 cycle

ORL

direct, A

OR ACC to direct byte

2 byte/1 cycle

ORL

direct, #data

OR immediate data to direct

byte

3 byte/2 cycle

SWAP

Swap nibbles within the ACC

1 byte/1 cycle

XRL

A, Rn

Exclusive-OR register to ACC

1 byte/1 cycle

XRL

A, direct

Exclusive-OR direct byte to

ACC

2 byte/1 cycle

Table 6.

Arithmetic instruction set (continued)

Mnemonic(1)

and use

Description

Length/cycles

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