EM3595-RTR datasheet(27/59 Pages) SILABS

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EM359x

Rev 1.0

4. EM359x System Overview

Figure 4.1 shows a detailed block diagram of the EM359x.

Figure 4.1. EM359x Block Diagram

The EM359x radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize

co-existence with other devices in the 2.4 GHz band (namely Wi-Fi and Bluetooth), and to minimize power

consumption. The receiver uses differential signal paths to reduce sensitivity to noise interference. Following RF

amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.

The digital section of the receiver uses a coherent demodulator to generate symbols for the hardware-based MAC.

The digital receiver also contains the analog radio calibration routines, and controls the gain within the receiver

path.

The radio transmitter uses an efficient architecture in which the data stream directly modulates the VCO frequency.

An integrated PA provides the output power. Digital logic controls Tx path and output power calibration. If the

EM359x is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the

external switching logic.

The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading

capacitors is required to establish the PLL local oscillator signal.

The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC provides hardware-based

IEEE 802.15.4-2003 packet-level filtering. It supplies an accurate symbol time base that minimizes the

synchronization effort of the Ember software and meets the protocol timing requirements. In addition, it provides

timer and synchronization assistance for the IEEE 802.15.4-2003 CSMA-CA algorithm.

The EM359x integrates hardware support for a packet trace module, which allows robust packet-based debug.

This element is a critical component of Ember Desktop, the Ember development environment, and provides

advanced network debug capability when used with the Ember Debug Adapter (ISA3).

ADC

RF_P,N

Program Flash

256/512 kB

Data

RAM

32/64 kB

HF crystal

OSC

LF crystal

OSC

General

Purpose

ADC

Serial Wire

and JTAG

debug

Internal LF

RC-OSC

GPIO multiplexor switch

Chip

manager

1.8V

Regulator

Bias

2nd level

Interrupt

controller

RF_TX_ALT_P,N

OSCA

OSCB

PA[7:0], PB[7:0], PC[7:0], PD[4:1], PE[3:0]

Encryption

acclerator

Always

Powered

Domain

ARM® CortexTM-M3

CPU with NVIC

and MPU

VREG_OUT

Watchdog

PA select

LNA

DAC

MAC

Baseband

Sleep

timer

POR

nRESET

General

purpose

timers

GPIO

registers

UART/SPI/

TWI

SYNTH

Internal HF

RC-OSC

TX_ACTIVE

Calibration

ADC

Packet Trace

CPU debug TPIU/

ITM/FPB/DWT/

ETM

1.25V

Regulator

VDD_CORE

USB

Device

SWCLK, JTCK

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