EM3595-RTR datasheet(31/59 Pages) SILABS

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EM359x

Rev 1.0

4.4.2. Resets

The EM359x resets are generated from a number of sources. Each of these reset sources feeds into central reset

detection logic that causes various parts of the system to be reset depending on the state of the system and the

nature of the reset event. Reset sources include:



Power-On-Resets (POR HV and POR LV)



nRESET Pin



Watchdog Reset



Software Reset



Option Byte Error



Debug Reset



JRST



Deep Sleep Reset

The EM359x records the last reset condition that generated a restart to the system. The Reset Generation module

responds to reset sources and generates reset signals, which vary based on the reset source and cause.

4.4.3. Clocks

The EM359x integrates four oscillators:



12 MHz RC oscillator: Used as the default system clock source when power is applied to the core domain.



24 MHz crystal oscillator: Requires an external 24 MHz crystal. Used as the system clock source when all

peripherals, including the radio peripheral, require the most accurate clock.



10 kHz RC oscillator: Provided as an internal timing reference



32.768 kHz crystal oscillator: Provided as an optional timing reference for on-chip timers.

4.4.4. System Timers

The EM359x contains three system timers:



Watchdog Timer: Can be enabled to provide protection against software crashes and ARM® CortexTM-M3

CPU lockup.



Sleep Timer: 32-bit timer dedicated to system timing and waking from sleep at specific times.



Event Timer: An ARM® standard system timer in the NVIC.

4.4.5. Power Management

The EM359x’s power management system is designed to achieve the lowest deep sleep current consumption

possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM359x has four

main sleep modes:



Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All

power domains remain fully powered and nothing is reset.



Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down

and the sleep timer is active.



Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this

mode the sleep timer cannot wake up the EM359x.



Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without

powering down the core domain. Instead, the core domain remains powered and all peripherals except the

system debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to

allow EM359x software to perform a deep sleep cycle while maintaining debug configuration such as

breakpoints.

The deep sleep modes consume less than 2 µA power. When in deep sleep the EM359x can be returned to the

running state in a number of ways. The wake sources are split depending on deep sleep 1 or deep sleep 2.

The RAM can optionally be configured to select banks of locations to be non-volatile. In deep sleep those banks

selected are powered by a low leakage internal regulator that remains on during deep sleep, powered from the

always-on supply.

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