DLPC910 datasheet(37/50 Pages) TI1

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DLPC910

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DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

Typical Application (continued)

8.2.1.1 Design Requirements

The DLPC910 interface is made up of several buses and controls signals as shown in the following list. The

LVDS input buses provides the means of loading data to the DLPC910 and the LVDS output buses provide the

data to DMD. Each input and output LVDS bus has an associated clock which clocks the data into the DLPC910

or into the DLP9000X. Row and Block control signals define the type of mirror clock pulse to use after all the

data is loaded into the DLP9000X.

•

LVDS differential inputs

–

DDC_DCLK 4 buses

–

DVALID 4 buses

–

DDC_DIN 4 buses

•

LVDS differential outputs. Refer to LVDS Output Bus Skew for recommendations on trace lengths.

–

DDC_DOUT 4 buses

–

DDC_DCLKOUT 4 buses

–

DDC_SCTRL 4 buses

•

Control output signals

–

DMD RESET

–

DMD SCP

•

Row and Block control input signals

–

ROWMD

–

ROWAD

–

BLKMD

–

BLKAD

–

RST2BLKZ

•

Control input signals

–

COMP_DATA

–

NS_FLIP

–

WDT_ENBLZ

–

PWR_FLOAT

–

LOAD4_ENZ

•

Status output signals

–

RST_ACTIVE

–

INIT_ACTIVE

–

ECP2_FINISHED

–

DMD_IRQ

•

Controller reset

–

CTRL_RSTZ

•

DLPR910 interface

–

PGM(4:0)

–

JTAG(3:0)

8.2.1.2 Detailed Design Procedure

After power is applied to the DLPC910, the APPS FPGA should monitor the ECP2_FINISHED signal to

determine when the DLPC910 has completed loading the configuration from the DLPR910. The APPS FPGA

next monitors the INIT_ACTIVE signal to determine when the DLPC910 has completed its internal initialization

routines and has configured the DMD for normal operation. An alternate method is to request the initialization

status using the I2C interface. Information regarding initialization, versions, and IDs can be requested through

this interface.

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