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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DLPC910 데이터시트(PDF) 15 Page - Texas Instruments |
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DLPC910 데이터시트(HTML) 15 Page - Texas Instruments |
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15 / 50 page  COMP_DATA/ NS_FLIP 50% DCLKIN tc 50% 50% tw(H) tw(L) 20% 80% tt tsu th VALID 50% DVALID DCLKIN DDR Data t sk Control Cycle 1 Cycle#CLKS/ ROW t w(H) t c t w(L) 50% 50% t t 80% 20% 50% t sk DLPC910 www.ti.com DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015 Timing Requirements (continued) (see (1)) MIN NOM MAX UNIT tsk Skew, DIN_A(15-0) to DCLKIN_A -100 100 ps Skew, DIN_B(15-0) to DCLKIN_B -100 100 Skew, DIN_C(15-0) to DCLKIN_C -100 100 Skew, DIN_D(15-0) to DCLKIN_D -100 100 Skew, DVALID_n to DCLKIN_n ↑ -100 100 Skew, BLK_MD BLK_AD to -100 100 DCLKIN_n ↑ (4) Skew, ROWMD or ROWAD to -100 100 DCLKIN_n ↑ (4) Skew, STEPVCC to DCLKIN ↑ (4) -100 100 (4) First edge of DDC_DIN*, ROW*, and BLK* should be synchronous to DVALID rising edge. Figure 1. Input Interface Timing Figure 2. Control Timing Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: DLPC910 |
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