L9663 datasheet(39/104 Pages) STMICROELECTRONICS

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L9663

Satellite interface

103

If the SID is used, a diagnostic bit (G bit) is also present in the SPI frame sent to the MCU.

This bit signals the occurrence of specific faults, namely an under voltage on the VAS

supply, or a parity check fault on a critical register(g) .

The data register containing SID bits and PSI5 sensor data is written with one single access:

data from the Manchester decoder is identified with reference to the time slot counter and

written in the same access when the information of the transmitting sensor is written.

Each failure case, CRC checksum and SID identification mismatch, can be forced via test

SPI commands through STS and STSR register after a special "self test" mode is entered

through an SPI command (see DCR (PROG) register for details).

3.7.3

Buffer empty check

As described in Section 3.3.2, the IC always checks that, after a valid data read, the code

1F0 is written in the buffer.

This feature is the "Buffer Empty check", implemented for safety: if the check fails a Buffer

Empty Fault is asserted and latched (BEx bits in SR2 register) and it is cleared after reading

through SPI.

In order to allow the μC to test this feature at startup or during normal operation, a Test of

buffer empty check is provided in the STSR register (bit0).

If this bit is set, after a read operation the old data is left in the buffer; in this way a buffer

empty fault is set and the μC can test the safety feature.

3.7.4

DOUTx path check

DOUTx paths can be checked against fault conditions through dedicated test SPI register

(STS register).

In order to test the input structures of the connected microcontroller, the L9663 features a

DOUTx test mode that allows test patterns to be applied on the two outputs DOUT1-

DOUT2. The test mode can be entered via SPI and the test patterns can also be controlled

via SPI commands. Test patterns can be composed only of static high or low signals, which

can be selected via SPI. For failsafe reasons only one channel at a time can be switched

into test mode.

g. The fault "clock error" is not included in the G bit because in this case the device enters immediately reset

state, if the bit REACTTIME of ADVSET2 register is '0' (default).

Table 9. Doutx test mode bit value

Bit

Name

Description

DOUTTP

Test Pattern:

1: Static output set to high on DOUTx, for which test mode is enabled

0: Static output set to low on DOUTx, for which test mode is enabled

9:5

DOUTSEL

Dout Test Mode Selection Bits:

10101: DOUT Test Mode Enabled for DOUT1 Output

10110: DOUT Test Mode Enabled for DOUT2 Output

All other bit patterns: DOUT Test Mode Disabled

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