Rev.4/08/02

SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers

© Copyright 2002 Sipex Corporation

6

DESCRIPTION

The SP3249E device meets the EIA/TIA-232 and

ITU-T V.28/V.24 communication protocols and

can be implemented in battery-powered, por-

table, or hand-held applications such as

notebook or palmtop computers. The SP3249E

device features Sipex's proprietary and patented

(U.S. #5,306,954) on-board charge pump

circuitry that generates

±5.5V RS-232 voltage

levels from a single +3.0V to +5.5V power

supply. The SP3249E device can operate at

a data rate of 250kbps fully loaded.

The SP3249E is a 5-driver/3-receiver device,

ideal for portable or hand-held applications.

The SP3249E device is an ideal choice for

power sensitive designs.

THEORY OF OPERATION

The SP3249E device is made up of three basic

circuit blocks: 1. Drivers, 2. Receivers, and

3. the Sipex proprietary charge pump.

Drivers

The drivers are inverting level transmitters that

convert TTL or CMOS logic levels to 5.0V EIA/

TIA-232 levels with an inverted sense relative to

the input logic levels. Typically, the RS-232

output voltage swing is +5.4V with no load and

+5V minimum fully loaded. The driver outputs

are protected against infinite short-circuits to

ground without degradation in reliability. These

drivers comply with the EIA-TIA-232F and all

previous RS-232 versions. Unused driver inputs

should be connected to GND or V

The drivers can guarantee a data rate of 250kbps

fully loaded with 3k

Ω in parallel with 1000pF,

ensuring compatibility with PC-to-PC commu-

nication software.

The slew rate of the driver output is internally

limited to a maximum of 30V/

µs in order to

meet the EIA standards (EIA RS-232D 2.1.7,

Paragraph 5). The transition of the loaded

output from HIGH to LOW also meets the

monotonicity requirements of the standard.

Figure 7 shows a loopback test circuit used to test

the RS-232 Drivers. Figure 8 shows the test

results of the loopback circuit with all five driv-

ers active at 120kbps with typical RS-232 loads

in parallel with 1000pF capacitors. Figure 6 shows

the test results where one driver was active at

250kbps and all five drivers loaded with an RS-

232 receiver in parallel with a 1000pF capacitor.

A solid RS-232 data transmission rate of 120kbps

provides compatibility with many designs in

personal computer peripherals and LAN appli-

cations.

Receivers

The receivers convert

±5.0V EIA/TIA-232

levels to TTL or CMOS logic output levels.

Since receiver input is usually from a transmission

line where long cable lengths and system

interference can degrade the signal, the inputs

have a typical hysteresis margin of 500mV. This

ensures that the receiver is virtually immune to

noisy transmission lines. Should an input be left

unconnected, an internal 5k

Ω pulldown resistor

to ground will commit the output of the receiver

to a HIGH state.

Figure 6. Interface Circuitry Controlled by

Microprocessor Supervisory Circuit

SP3249E

3

1

4

GND

C1+

C1-

C2+

C2-

V+

V-

0.1

µF

0.1

µF

0.1

µF

+

C2

C5

C1

+

+

C3

C4

+

+

0.1

µF

0.1

µF

2

5k

Ω

5k

Ω

5k

Ω

24

23

22

21

20

18

5

6

7

8

9

11

RS-232

OUTPUTS

RS-232

INPUTS

T

R

R

T

T

T

T

T

R

R

R

R

UART

or

Serial

µC

TxD

RTS

DTR

RxD

CTS

DSR

DCD

RI

19

17

10

12

T

T

T

T

13

15

14

16