전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SP3249E 데이터시트(PDF) 7 Page - Sipex Corporation

부품명 SP3249E
상세설명  Intelligent 3.0V to 5.5V RS-232 Transceivers
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  SIPEX [Sipex Corporation]
홈페이지  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP3249E 데이터시트(HTML) 7 Page - Sipex Corporation

Back Button SP3249E Datasheet HTML 3Page - Sipex Corporation SP3249E Datasheet HTML 4Page - Sipex Corporation SP3249E Datasheet HTML 5Page - Sipex Corporation SP3249E Datasheet HTML 6Page - Sipex Corporation SP3249E Datasheet HTML 7Page - Sipex Corporation SP3249E Datasheet HTML 8Page - Sipex Corporation SP3249E Datasheet HTML 9Page - Sipex Corporation SP3249E Datasheet HTML 10Page - Sipex Corporation SP3249E Datasheet HTML 11Page - Sipex Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 14 page
background image
7
Rev.4/08/02
SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers
© Copyright 2002 Sipex Corporation
Charge Pump
The charge pump is a Sipex–patented design
(U.S. #5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies.
The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V
CC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting (Figure 13). A descrip-
tion of each phase follows.
Phase 1 (Figure 11)
— V
SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
1 and C2 are initially charged to VCC.
C
l
+ is
then switched to GND and the charge in C
1
is
transferred to C
2
. Since C
2
+ is connected to
V
CC, the voltage potential across capacitor C2 is
now 2 times V
CC.
Figure 7. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
Phase 2 (Figure 12)
— V
SS transfer — Phase two of the clock
connects the negative terminal of C
2 to the VSS
storage capacitor and the positive terminal of C
2
to GND. This transfers a negative generated
voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C
3, the positive side of capacitor C1 is switched
to V
CC and the negative side is connected to
GND.
Phase 3 (Figure 14)
Figure 8. Loopback Test Circuit Result at 120kbps
(All Drivers Fully Loaded)
Figure 9. Loopback Test Circuit result at 250kbps
(All Drivers Fully Loaded)
SP3249E
TxIN
TxOUT
C1+
C1-
C2+
C2-
V+
V-
VCC
0.1
µF
0.1
µF
0.1
µF
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
µF
0.1
µF
LOGIC
INPUTS
VCC
5k
RxIN
RxOUT
LOGIC
OUTPUTS
GND
1000pF



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com