BQ76PL536APAPR datasheet(53/74 Pages) TI1

53 / 74 page

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

Table 25. CONFIG_CUVT Register Field Descriptions

Bit

Field

Type

Reset

Description

µs/ms

Determines the units of the delay time, microseconds or

milliseconds

0 = Microseconds

1 = Milliseconds

6-5

Reserved

4-0

CUVD[n]

0x01 = 100; each binary increment adds 100 until 0x1f = 3100

Note: When this register is programmed to 0x00, the delay

becomes 0 s AND the CUV state is NOT latched in the

CUV_FAULT register. In this operating mode, the undervoltage

state for a cell is virtually instantaneous in the CUV_FAULT

dangerous cell undervoltage condition.

7.6.30 CONFIG_OT Register (0x46)

The CONFIG_OT register holds the configuration of the overtemperature thresholds for the two TS inputs.

For each respective nibble (OT1 or OT2), the value 0x0 disables this function. Other settings program a trip

threshold. See the Ratiometric Sensing section for details of setting this register. Values above 0x0b are illegal

and should not be used.

Figure 53. CONFIG_OT Register

OT2[3]

OT2[2]

OT2[1]

OT2[0]

OT1[3]

OT1[2]

OT1[1]

OT1[0]

7.6.31 CONFIG_OTT Register (0x47)

The CONFIG_OTT register determines cell overtemperature detection delay time.

0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds.

NOTE

When this register is programmed to 0x00, the delay becomes 0 s AND the OT state is

NOT latched in the ALERT_STATUS register. In this operating mode, the overtemperature

state for a TSn input is virtually instantaneous in the register. This mode may cause

system firmware to miss a dangerous overtemperature condition.

Figure 54. CONFIG_OTT Register

COTD[7]

COTD[6]

COTD[5]

COTD[4]

COTD[3]

COTD[2]

COTD[1]

COTD[0]

7.6.32 USERx Register (0x48–0x4b) (USER1–4)

The four USER registers can be used to store user data. The part does not use these registers for any internal

function. They are provided as convenient storage for user S/N, date of manufacture, and so forth.

Figure 55. USERx Register

USER[7]

USER[6]

USER[5]

USER[4]

USER[3]

USER[2]

USER[1]

USER[0]

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