TMS320C6743CPTP2 datasheet(95/151 Pages) TI1

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TMS320C6743

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SPRS565D – APRIL 2009 – REVISED JUNE 2014

6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing

Table 6-44 and Table 6-45 assume testing over recommended operating conditions (see Figure 6-29 and

Figure 6-30).

Table 6-44. McASP1 Timing Requirements(1)(2)

NO.

MIN

MAX

UNIT

Cycle time, AHCLKR1 external, AHCLKR1 input

tc(AHCLKRX)

Cycle time, AHCLKX1 external, AHCLKX1 input

Pulse duration, AHCLKR1 external, AHCLKR1 input

12.5

tw(AHCLKRX)

Pulse duration, AHCLKX1 external, AHCLKX1 input

12.5

Cycle time, ACLKR1 external, ACLKR1 input

greater of 2P or 25

tc(ACLKRX)

Cycle time, ACLKX1 external, ACLKX1 input

greater of 2P or 25

Pulse duration, ACLKR1 external, ACLKR1 input

12.5

tw(ACLKRX)

Pulse duration, ACLKX1 external, ACLKX1 input

12.5

Setup time, AFSR1 input to ACLKR1 internal(3)

10.4

Setup time, AFSX1 input to ACLKX1 internal

10.4

Setup time, AFSR1 input to ACLKR1 external input (3)

2.6

tsu(AFSRX-ACLKRX)

Setup time, AFSX1 input to ACLKX1 external input

2.6

Setup time, AFSR1 input to ACLKR1 external output (3)

2.6

Setup time, AFSX1 input to ACLKX1 external output

2.6

Hold time, AFSR1 input after ACLKR1 internal(3)

-1.9

Hold time, AFSX1 input after ACLKX1 internal

-1.9

Hold time, AFSR1 input after ACLKR1 external input (3)

0.7

th(ACLKRX-AFSRX)

Hold time, AFSX1 input after ACLKX1 external input

0.7

Hold time, AFSR1 input after ACLKR1 external output (3)

0.7

Hold time, AFSX1 input after ACLKX1 external output

0.7

Setup time, AXR1[n] input to ACLKR1 internal (3)

10.4

Setup time, AXR1[n] input to ACLKX1 internal(4)

10.4

Setup time, AXR1[n] input to ACLKR1 external input (3)

2.6

tsu(AXR-ACLKRX)

Setup time, AXR1[n] input to ACLKX1 external input (4)

2.6

Setup time, AXR1[n] input to ACLKR1 external output (3)

2.6

Setup time, AXR1[n] input to ACLKX1 external output (4)

2.6

Hold time, AXR1[n] input after ACLKR1 internal(3)

-1.8

Hold time, AXR1[n] input after ACLKX1 internal (4)

-1.8

Hold time, AXR1[n] input after ACLKR1 external input (3)

0.5

th(ACLKRX-AXR)

Hold time, AXR1[n] input after ACLKX1 external input (4)

0.5

Hold time, AXR1[n] input after ACLKR1 external output (3)

0.5

Hold time, AXR1[n] input after ACLKX1 external output (4)

0.5

(1)

ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

P = SYSCLK2 period

(3)

McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1

(4)

McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1

Peripheral Information and Electrical Specifications

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