TABLE 5. Mode Programming (Continued)

ADC12038

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

Mode Selected

(Current)

DO Format

(next Conversion

Cycle)

ADC12034

DI0

DI1

DI2

DI3

DI4

DI5

DI6

ADC12030

and

DI0

DI1

DI2

DI3

DI4

DI5

ADC12032

H

H

L

L

H

H

H

L

Acquisition Time — 34 CCLK Cycles

No Change

L

L

L

L

HHHH

User Mode

No Change

H

X

X

X

HHHH

Test Mode

No Change

(CH1–CH7 become Active Outputs)

Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode.

X = Don’t Care

TABLE 6. Conversion/Read Data Only Mode Programming

CS

CONV

PD

Mode

L

L

L

See Table 5 for Mode

L

H

L

Read Only (Previous DO Format). No Conversion.

H

X

L

Idle

X

X

H

Power Down

X = Don’t Care

TABLE 7. Status Register

Status Bit

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

Location

Status Bit

PU

PD

Cal

8 or 9

12 or 13

16 or 17

Sign

Justification

Test Mode

Device Status

DO Output Format Status

Function

“High”

indicates a

Power Up

Sequence

is in

progress

“High”

indicates a

Power

Down

Sequence

is in

progress

“High”

indicates

an

Auto-Cal

Sequence

is in

progress

“High”

indicates

an8or9

bit format

“High”

indicates a

12 or 13

bit format

“High”

indicates a

16 or 17

bit format

“High”

indicates

that the

sign bit is

included.

When

“Low” the

sign bit is

not

included.

When “High”

the

conversion

result will be

output MSB

first. When

“Low” the

result will be

output LSB

first.

When “High”

the device is

in test mode.

When “Low”

the device is

in user

mode.

Application Hints

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The example in Figure 7 shows a typical sequence of events

after the power is applied to the ADC12030/2/4/8:

The first instruction input to the A/D via DI initiates Auto Cal.

The data output on DO at that time is meaningless and is

completely random. To determine whether the Auto Cal has

been completed, a read status instruction is issued to the

A/D. Again the data output at that time has no significance

since the Auto Cal procedure modifies the data in the output

shift register. To retrieve the status information, an additional

read status instruction is issued to the A/D. At this time the

status data is available on DO. If the Cal signal in the status

word, is low Auto Cal has been completed. Therefore, the

next instruction issued can start a conversion. The data

output at this time is again status information. To keep noise

from corrupting the A/D conversion, status can not be read

during a conversion. If CS is strobed and is brought low

during a conversion, that conversion is prematurely ended.

EOC can be used to determine the end of a conversion or

the A/D controller can keep track in software of when it would

be appropriate to comnmunicate to the A/D again. Once it

has been determined that the A/D has completed a conver-

sion, another instruction can be transmitted to the A/D. The

data from this conversion can be accessed when the next

instruction is issued to the A/D.

Note, when CS is low continuously it is important to transmit

the exact number of SCLK cycles, as shown in the timing

diagrams. Not doing so will desynchronize the serial com-

munication to the A/D. (See Section 1.3.)

01135436

FIGURE 7. Typical Power Supply Power Up Sequence

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