TABLE 4. Interupt Vector Table

Arbitration

Vector (Note 32)

Ranking

Source

Description

Address

Hi-Low Byte

(1) Highest

Software

INTR Instruction

0yFE–0yFF

(2)

Reserved

0yFC–0yFD

(3)

External

Pin G0 Edge

0yFA–0yFB

(4)

Timer T0

Underflow

0yF8–0yF9

(5)

Timer T1

T1A/Underflow

0yF6–0yF7

(6)

Timer T1

T1B

0yF4–0yF5

(7)

MICROWIRE/PLUS

BUSY Low

0yF2–0yF3

(8)

Reserved

0yF0–0yF1

(9)

Reserved

0yEE–0yEF

(10)

Reserved

0yEC–0yED

(11)

Timer T2

T2A/Underflow

0yEA–0yEB

(12)

Timer T2

T2B

0yE8–0yE9

(13)

Timer T3

T3A/Underflow

0yE6–0yE7

(14)

Timer T3

T3B

0yE4–0yE5

(15)

Port L/Wakeup

Port L Edge

0yE2–0yE3

(16) Lowest

Default

VIS Instr. Execution

0yE0–0yE1

without Any Interrupts

Note 32: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-

dress of a block. In this case, the table must be in the next block.

VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

mains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

Figure 15 illustrates the different steps performed by the VIS

instruction.

Figure 16 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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