COP888GD datasheet(22/42 Pages) NSC

22 / 42 page

A/D Converter (Continued)

The A/D converter takes 17 A/D clock cycles to complete a

conversion. Thus the minimum A/D conversion time for the

device is 10.2 µs when a prescaler of 6 has been selected.

The 17 A/D clock cycles needed for conversion consist of 1

cycle at the beginning for reset, 7 cycles for sampling, 8

cycles for converting, and 1 cycle for loading the result into

the A/D result register (ADRSLT). This A/D result register is a

read-only register. The user cannot write into ADRSLT.

The ADBSY flag provides an A/D clock inhibit function, which

saves power by powering down the A/D when it is not in use.

Note: The A/D converter is also powered down when the device is in either

the HALT or IDLE modes. If the A/D is running when the device enters

the HALT or IDLE modes, the A/D powers down and then restarts the

conversion with a corrupted sampled voltage (and thus an invalid re-

sult) when the device comes out of the HALT or IDLE modes.

Analog Input and Source Resistance Considerations

Figure 13 shows the A/D pin model in single ended mode.

The differential mode has a similar A/D pin model. The leads

to the analog inputs should be kept as short as possible.

Both noise and digital clock coupling to an A/D input can

cause conversion errors. The clock lead should be kept

away from the analog input line to reduce coupling. The A/D

channel input pins do not have any internal output driver cir-

cuitry connected to them because this circuitry would load

the analog input signals due to output buffer leakage current.

Source impedances greater than 3 k

Ω on the analog input

lines will adversely affect the internal RC charging time dur-

ing input sampling. As shown in

Figure 13, the analog switch

to the DAC array is closed only during the 7 A/D cycle

sample time. Large source impedances on the analog inputs

may result in the DAC array not being charged to the correct

voltage levels, causing scale errors.

If large source resistance is necessary, the recommended

solution is to slow down the A/D clock speed in proportion to

the source resistance. The A/D converter may be operated

at the maximum speed for R

S less than 3 kΩ. For RS greater

than 3 k

Ω, A/D clock speed needs to be reduced. For ex-

ample, with R

S = 6kΩ, the A/D converter may be operated

at half the maximum speed. A/D converter clock speed may

be slowed down by either increasing the A/D prescaler

divide-by or decreasing the CKI clock frquency. The A/D

minimum clock speed is 100 kHz.

Interrupts

INTRODUCTION

Each device supports eleven vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Each of the 11 maskable inputs has a fixed arbitration rank-

ing and vector.

Figure 14 shows the Interrupt Block Diagram.

DS100076-18

*The analog switch is closed only during the sample time.

FIGURE 13. A/D Pin Model (Single Ended Mode)

COP888GD 데이터시트(PDF) 22 Page - National Semiconductor (TI)

COP888GD 데이터시트(HTML) 22 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

데이터시트 다운로드

링크 URL