PC87413 datasheet(200/257 Pages) NSC

200 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

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200

Revision1.2

9.3.31

Sleep State Configuration Register (SLP_ST_CFG)

This register controls the operation of the Sleep Type encoding. It is reset by hardware to 00h.

Power Well:VPP

Location:Bank 2, Offset 16h

Type:

Varies per bit

Bit

43210

Name

LOCK

_SLP_ENC

Reserved

EXT_ST

_SELECT

S3I

_VDD_ON

_SELECT

Reset

00000

Bit

Type

Description

R/W1S LOCK_SLP_ENC (Lock Sleep Type Encoding). When set to 1, this bit locks the S0_SLP_TYP to

S5_SLP_TYP and the SLP_ST_CFG registers by disabling the writing to them (including to the

LOCK_SLP_ENC bit itself). Once set, this bit can be cleared either by VDD Power-Up reset (or

Hardware reset) or by VSB Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register

(see Section 6.3.4 on page 128). In addition, this bit is cleared by setting the UNLOCKS bit in the

ACBLKCTL register (PC87413 and PC87417).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-3

Reserved.

R/W or

EXT_ST_SELECT (External Sleep State Select). Selects the source of the current sleep states.

0: SLP_TYPx field in the PM1b_CNT_HIGH register (see Section 9.4.7 on page 208); (default)

1: SLPS3 and SLPS5 signals from an external ACPI controller (see also the EXTSTMUX bit in the

SIOCF3 register, Section 3.7.4 on page 51)

R/W or

S3I_VDD_ON (VDD-On in S3I Select). Selects the state of the VDD power supply in the S3I current

sleep state.

0: VDD power supply Off (default)

1: VDD power supply On

R/W or

S4_SELECT (S4 Select). Selects whether the sleep state S4 (if supported) is included in either S3I or

S45 current sleep states.

0: S45 = S5 or S4 (default)

1: S3I = S3 or S4

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