| 전자부품 데이터시트 검색엔진 |
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PC87413 데이터시트(PDF) 202 Page - National Semiconductor (TI) |
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PC87413 데이터시트(HTML) 202 Page - National Semiconductor (TI) |
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202 / 257 page ![]() 9.0 System Wake-Up Control (SWC) (Continued) www.national.com 202 Revision1.2 9.3.33 Watchdog Control Register (WDCTL) This register contains the control bits for the watchdog. It is reset by hardware to 00h. Power Well:VSB Location: Bank 3, Offset 10h Type: Varies per bit 9.3.34 Watchdog Time-Out Register (WDTO) This register contains the watchdog time-out period. It is reset by hardware to 01h. Power Well:VSB Location: Bank 3, Offset 11h Type: R/W Bit 76 5 43210 Name SW_WD _TRG Reserved WDEN Reset 0 0 0 00000 Bit Type Description 7 R/W SW_WD_TRG (Software Watchdog Trigger). Writing ‘1’ to this bit triggers the watchdog to start a new count. This bit then returns to ‘0’ (read always returns ‘0’). 0: Inactive (default) 1: Triggers a new watchdog count 6-1 Reserved. 0 R/W1S WDEN (Watchdog Enable). When set to 1, this bit enables the watchdog function. Once set, this bit can be cleared either by VDD Power-Up reset, or by VSB Power-Up reset. 0: Watchdog disabled (default) 1: Watchdog enabled Bit 76 5 43210 Name Watchdog Time-Out Data Reset 0 0 0 00001 Bit Description 7-0 Watchdog Time-Out Data. The load value for the watchdog down counter. The value defines the time-out in minutes for a span of: 1 to 255 minutes. The 00h value is reserved. |
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