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PCI9060ES 데이터시트(PDF) 27 Page - List of Unclassifed Manufacturers

부품명 PCI9060ES
상세설명  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PDF  192 Pages
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제조업체  ETC [List of Unclassifed Manufacturers]
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PCI9060ES 데이터시트(HTML) 27 Page - List of Unclassifed Manufacturers

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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
©PLX Technology, Inc., 1997
Page 18
Version 1.02
3.5 RESPONSE TO FIFO FULL/EMPTY
Table 3-6 lists the response of the PCI 9080 to full and empty FIFOs.
Table 3-6. Response to FIFO Full/Empty
Mode
Direction
FIFO
PCI Side
Local Side
Full
No action
De-assert READYo#
Direct Master Write
Local to PCI
Empty
De-assert REQ# (off PCI bus)
No action
Full
De-assert REQ# or throttle IRDY#
No action
Direct Master Read
PCI to Local
Empty
No action
De-assert READYo#
Full
Disconnect or throttle TRDY#
No action
Direct Slave Write
PCI to Local
Empty
No action
De-assert LHOLD, assert BLAST# (see
Note)
Full
No action
De-assert LHOLD, assert BLAST# (see
Note)
Direct Slave Read
Local to PCI
Empty
Throttle TRDY#
No action
Full
No action
De-assert LHOLD, assert BLAST#
Local to PCI
Empty
De-assert REQ#
No action
Full
De-assert REQ#
No action
DMA
PCI to Local
Empty
No action
De-assert LHOLD, assert BLAST#
Note:
De-assert of LHOLD depends on MARBR[21].
3.6 DIRECT DATA TRANSFER MODES
Figure 3-4 and Figure 3-5 illustrate the direct data
transfer modes. Refer also to Table 3-6 for responses to
full and empty FIFOs.
 


 


 

 
 
  
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*+ ,
 

- ,.    / # %  &'(  "  0  '+
/ ,.     % # %  "  #   '+
,& 12  '+ *%  % # %  + '  
 % %  "#!  '+
Figure 3-4. Direct Master, Direct Slave, and DMA




%!!  
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(!%1   %
    % 
(!%1
(!%1 0
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(!%1 3
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(!%1 6
(!%1 7
  
  
  
  
  
 
Figure 3-5. Mailbox/Doorbell Message Passing
3.6.1 Direct Master Operation (Local Master
to PCI Target)
PCI 9080 supports the direct access of the PCI bus by
the local processor or an intelligent controller. Master
mode must be enabled in the PCI Command Register.
Five registers are used to define local to PCI access:
•
Range
•
Local Base Address for Direct Master to PCI
Memory Register
•
Local Base Address for Direct Master to PCI IO/CFG
Register



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