PCI9060ES datasheet(68/192 Pages) ETC

68 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 59

Version 1.02

4.3.11 (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local,

Runtime, and DMA Registers

Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and

DMA Registers

Field

Description

Read

Write

Value after Reset

Memory Space Indicator. Value of 0 indicates register maps into memory space.

Value of 1 indicates register maps into I/O space.

Note:

Hardcoded to 1.

Yes

Reserved.

Yes

7:2

I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA

registers. (Default is 256 bytes)

Note:

Hardcoded to 0.

Yes

31:8

I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA

registers.

Yes

4.3.12 (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to

Local Address Space 0

Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address

Space 0

Field

Description

Read

Write

Value after

Reset

Memory Space Indicator. Value of 0 indicates register maps into memory space.

Value of 1 indicates register maps into I/O space.

(Specified in LAS0RR register.)

Yes

2:1

Location of Register (If memory space). Location values:

00—Locate anywhere in 32 bit memory address space

01—Locate below 1 MB memory address space

10—Locate anywhere in 64 bit memory address space

11—Reserved

(Specified in LAS0RR register.)

If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.

Yes

Mem: No

I/O:

bit 1 no,

bit 2 yes

Prefetchable (If memory space). Value of 1 indicates there are no side effects on

reads. This bit reflects the value of bit 3 in the LAS0RR register and provides only

status to the system. This bit has no effect on the operation of the PCI 9080.

Prefetching features of this address space are controlled by the associated Bus

Region Descriptor Register.

(Specified in LAS0RR register.)

If I/O Space, bit 3 is included in the base address.

Yes

Mem: No

I/O: Yes

31:4

Memory Base Address. Memory base address for access to Local Address Space

Yes

Note:

PCIBAR2 can be enabled or disabled by setting or clearing bit 0 in the LAS0BA register.

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