PCI9060ES datasheet(38/192 Pages) ETC

38 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 29

Version 1.02

The local processor or PCI requires DMA. PCI 9080 is

master on both the PCI and local buses. Direct Slave or

Direct Master pre-empts DMA.

PCI 9080 releases the PCI bus if one of the following

occurs (refer to Figure 3-15):

•

FIFO full

•

Terminal count reached

•

PCI Latency Timer (PCI:0Dh)(LOC:0Dh) expires

(refer to Table 4-16[7:0])—normally programmed by

the Host PCI BIOS— and PCI GNT# de-asserts

•

PCI host asserts STOP

•

Direct Master request pending

% &

Figure 3-15. DMA, PCI to Local

PCI 9080 releases the local bus if one of the following

occurs (refer to Figure 3-16):

•

FIFO empty

•

Terminal count reached

•

Local Bus Latency Timer (PCI:08h or PCI:ACh)

(LOC:88h or LOC:12Ch) expires (refer to

Table 4-35[7:0])

•

BREQ# input asserted

•

Direct Slave request pending

Figure 3-16. DMA, Local to PCI

3.7.2 Chaining Mode DMA

In Chaining mode DMA, the Host Processor or the Local

Processor sets up descriptor blocks in local or host

memory that are composed of a PCI address, local

address, transfer count, transfer direction, and address

of the next descriptor block (refer to Figure 3-18). Host

or Local Processor then sets up the address of the initial

descriptor block in the descriptor pointer register of the

PCI 9080 and initiates the transfer by setting a control

bit. PCI 9080 loads the first descriptor block and initiates

the data transfer. PCI 9080 continues to load descriptor

blocks and transfer data until it detects the end of chain

bit is set in the next descriptor pointer register. PCI 9080

can be programmed to interrupt the local processor by

setting the "Interrupt after Terminal Count" bit or PCI

host upon completion of each block transfer and after all

block transfers are complete (done) (refer to Figure

3-17). If chaining descriptors are located in local

memory, the DMA controller can be programmed to

clear the transfer size at the completion of each DMA.

(Refer to DMA Clear Count mode, Table 4-62[16] and

Table 4-67[16].)

Notes: In Chaining mode DMA, the descriptor includes

PCI address, local address, transfer size and the next

descriptor

pointer.

(PCI:84h,

location

104-PCI:90h,

location 110D). The descriptor pointer register contains

the end of chain bit, direction of transfer, next descriptor

address, and next descriptor location.

DMA descriptor can be on the local memory or PCI

memory, or both (first descriptor on local memory, and

second descriptor on PCI memory).

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