PCI9060ES datasheet(105/192 Pages) ETC

105 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 96

Version 1.02

5.4 J BUS MODE PIN OUT

Table 5-7. J Bus Mode Interface Pin Description

J Bus Mode

Symbol

Signal Name

Total

Pins

Type

Number

Function

ALE

Address Latch Enable

8 mA

161

Asserted during the address phase and negated before the data

phase.

ADS#

Address Strobe

I/O

12 mA

154

Indicates the valid address and the start of a new bus access.

Asserted for the first clock of a bus access.

BLAST#

Burst Last

I/O

8 mA

155

Signal driven by the current local bus master to indicate the last

transfer in a bus access.

BTERM#

Burst Terminate

146

For processors that burst up to four Lwords. If Bterm is disabled

through the PCI 9080 configuration registers, PCI 9080 also bursts

up to four Lwords. If enabled, PCI 9080 continues to burst until a

BTERM# input is asserted. BTERM# is a ready input that breaks up

a burst cycle and causes another address cycle to occur. Used in

conjunction with the PCI 9080 programmable wait state generator.

DEN#

Data Enable

I/O

12 mA

145

As an input, DEN# must only be asserted during data phases. For

processor systems in which ADS# is not asserted during the data

phase, DEN# can be pulled high.

As an output, DT/R# is used in conjunction with DEN# to provide

control for data transceivers attached to the local bus.

DT/R#

Data

Transmit/Receive

12 mA

138

Used in conjunction with DEN# to provide control for data transceivers

attached to the local bus. When asserted the signal indicates the PCI

9080 receives data.

LW/R#

Write/Read

I/O

12 mA

137

Asserted low for reads and high for writes.

LABS[3:2]

Address Bus Burst

I/O

8 mA

162,163

Carries the word address of the 32 bit memory address. These bits

are incremented during a burst access.

LAD[31:0]

Address/Data Bus

I/O

8 mA

136, 135,

133-125,

122-115,

113-106,

103-99

During the address phase, the bus carries the upper 30 bits of the

physical address bus. During the data phase, the bus carries 32 bits

of data.

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