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PCI9060ES 데이터시트(PDF) 163 Page - List of Unclassifed Manufacturers

부품명 PCI9060ES
상세설명  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PDF  192 Pages
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제조업체  ETC [List of Unclassifed Manufacturers]
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PCI9060ES 데이터시트(HTML) 163 Page - List of Unclassifed Manufacturers

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SECTION 8
PCI 9080
TIMING DIAGRAMS
©PLX Technology, Inc., 1997
Page 154
Version 1.02
ADDR
CMD
BYTE ENABLES
ADDR
D0
D0
D1 D2
DIRECT SLAVE PROCEEDS
DIRECT MASTER READ
DIRECT SLAVE READ
DIRECT MASTER WILL NOT GAIN PCI BUS UNTIL DIRECT SLAVE ACCESS COMPLETES
(GNT# ASSERTED , FRAME# DE-ASSERTED, IRDY# DE-ASSERTED)
<-- DIRECT SLAVE- BREQo TIMER STARTS
NO DIRECT MASTER READY
D3
D1
D2
0ns
250ns
500ns
750ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
REQ#
LCLK
LHOLD
LHOLDA
ADS#
LA[31:2]
LD[31:0]
READYo#
READYi#
BREQo
BREQo timer expires and asserts BREQo
Note: For partial deadlock, PCI retry timer bits [31:28]
to indicate potential deadlock condition.
of the Local Bus Region Descriptor Register can be
used to issue RETRYs to the PCI Master attempting
External logic backs off Direct Master transfer and
the Direct Slave access.
asserts LHOLDA to grant the local bus for a Direct
Slave transfer.
Refer to Section 3, “Functional Description,” for
a description of deadlock.
Timing Diagram 8-51. (C Mode) BREQo and Deadlock



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