CS5530 datasheet(113/241 Pages) NSC

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Functional Description (Continued)

3.7

XPRESSAUDIO

Through XpressAUDIO, the CS5530 offers a combined

hardware/software support solution to meet industry stan-

dard audio requirements. XpressAUDIO uses Virtual Sys-

tem Architecture (VSA) technology along with additional

hardware features to provide the necessary support for

industry standard 16-bit stereo synthesis and OPL3 emu-

lation.

The hardware portion of XpressAUDIO is for transporting

streaming audio data to/from the system memory and an

AC97 codec. This hardware includes:

• Six (three inbound/three outbound) buffered PCI bus

mastering engines that drive specific AC97 interface

slots.

• Interfaces to AC97 codecs (e.g., LM4548) for audio

input/output.

Additional hardware provides the necessary functionality

for VSA technology. This hardware includes the ability to:

• Generate an SMI to alert software to update required

data. An SMI is generated when either audio buffer is

half empty or full. If the buffers become completely

empty or full, the Empty bit is asserted.

• Generate an SMI on I/O traps.

• Trap accesses for sound card compatibility at either I/O

Port 220h-22Fh, 240h-24Fh, 260h-26Fh, or 280h-

28Fh.

• Trap accesses for FM compatibility at I/O Port 388h-

38Bh.

• Trap accesses for MIDI UART interface at I/O Port

300h-301h or 330h-331h.

• Trap accesses for serial input and output at COM2 (I/O

Port 2F8h-2FFh) or COM4 (I/O Port 2E8h-2EFh).

• Support trapping for low (I/O Port 00h-0Fh) and/or high

(I/O Port C0h-DFh) DMA accesses.

• Support hardware status register reads in CS5530,

minimizing SMI overhead.

• Support is provided for software-generated IRQs on

IRQ 2, 3, 5, 7, 10, 11, 12, 13, 14, and 15.

Included in the following subsections are details regarding

the registers used for configuring the audio interface. The

registers are accessed through F3 Index 10h, the Base

Address Register (F3BAR) in Function 3. F3BAR sets the

base address for XpressAUDIO support registers as

shown in Table 3-61.

3.7.1

Subsystem Data Transport Hardware

The data transport hardware can be broadly divided into

two sections: bus mastering and the codec interface.

3.7.1.1

Audio Bus Masters

The CS5530 audio hardware includes six PCI bus mas-

ters (three for input and three for output) for transferring

digitized audio between memory and the external codec.

With these bus master engines, the CS5530 off-loads the

CPU and improves system performance.

The programming interface defines a simple scat-

ter/gather mechanism allowing large transfer blocks to be

scattered to or gathered from memory. This cuts down on

the number of interrupts to and interactions with the CPU.

Table 3-61. Base Address Register (F3BAR) for XpressAUDIO Registers

Bit

Description

F3 Index 10h-13h

Base Address Register — F3BAR (R/W)

Reset Value = 00000000h

This register sets the base address of the memory mapped audio interface control register block. This is a 4 KB block of registers

used to control the audio FIFO and codec interface, as well as to support SMIs produced by VSA technology. Bits [11:0] are read only

(0000 0000 0000), indicating a 4 KB memory address range. Refer to Table 4-20 for the bit formats and reset values of XpressAUDIO

registers.

31:12

Audio Interface Base Address

11:0

Address Range (Read Only)

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