CS9210 datasheet(10/39 Pages) NSC

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Revision 3.2

Signal Definitions (Continued)

DISPOFF#

131

(12 mA)

Disables Panel

When this output is asserted low, it indicates that the LCD panel

should be disabled.

FP_VDDEN

130

(12 mA)

Controls LCD VDD FET

When this output is asserted high, voltage should be applied to the

panel. This signal is intended to control a power FET to the LCD

panel.

FP_VCONEN

129

(12 mA)

Controls LCD Bias Voltage Enable

When this output is asserted high, the contrast voltage (VCON) should

be applied to the panel.

2.2.3

Flat Panel Interface Signals (Continued)

Signal Name

Pin No.

Type

(Drive)

Description

2.2.4

Memory Interface Signals

Signal Name

Pin No.

Type

(Drive)

Description

MA_A[9:0]

23-32

(4 mA)

DRAM Bank A Address Bus

The address bus for Bank A of the DRAM.

MD_A[15:0]

33-35,

39-51

I/O

(4 mA)

DRAM Bank A Data Bus

The data bus for Bank A of the DRAM.

MA_B[9:0]

95-92,

88-83

(4 mA)

DRAM Bank B Address Bus

The address bus for Bank B of the DRAM.

MD_B[15:0]

82-74,

70-64

I/O

(4 mA)

DRAM Bank B Data Bus

The data bus for Bank B of the DRAM.

OEA#

(4 mA)

DRAM Bank A Output Enable

The output enable for Bank A of the DRAM.

OEB#

(4 mA)

DRAM Bank B Output Enable

The output enable for Bank B of the DRAM.

RASA#

(4 mA)

DRAM Bank A Row Address Strobe

The row address strobe for Bank A of the DRAM.

RASB#

(4 mA)

DRAM Bank B Row Address Strobe

The row address strobe for Bank B of the DRAM.

UCASA#

(4 mA)

DRAM Bank A High Byte Column Address Strobe

The column address strobe for the upper eight bits of data for Bank A

of the DRAM.

LCASA#

(4 mA)

DRAM Bank A Low Byte Column Address Strobe

The column address strobe for the lower eight bits of data for Bank A

of the DRAM.

UCASB#

(4 mA)

DRAM Bank B High Byte Column Address Strobe

The column address strobe for the upper eight bits of data for Bank B

of the DRAM.

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