CS9210 datasheet(17/39 Pages) NSC

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Revision 3.2

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Functional Description (Continued)

The read and write protocols for the serial interface are

described in Table 3-5 and illustrated in Figures 3-3 and 3-

4. The protocol begins with the assertion of the SCS

input, followed by one start bit and three command bits.

Only two commands are defined, one for read and one for

write. The read protocol continues with one idle bit and

eightbits ofreaddataonSDO.The writeprotocolcontin-

ues with eight bits of write data on SDIN and one idle bit.

The deassertion of the SCS input for one SCLK cycle is

required to end the transaction.

Note that data driven into the CS9210 is shown changing

on the falling edge of SCLK. In general, this is a good

practice to avoid hold time problems that might occur if the

data were changing near the rising edge of SCLK. The

CS9210 samples the serial interface input signals with the

rising edge of SCLK. Data driven on the SDO output by

the CS9210 changes on the rising edge of SCLK.

Figure 3-3. Serial Interface Read Cycle Timing Diagram

Figure 3-4. Serial Interface Write Cycle Timing Diagram

Table 3-5. Serial Interface Read/Write Sequences

Cycle(s)

Read Sequence with SCS = “1”

Write Sequence with SCS = “1”

1 Start bit

SDIN = “1”

1 Start bit

SDIN = “1”

3 Command bits

SDIN = “000”

3 Command bits

SDIN = “001”

8 Address bits

ex: SDIN = "01110100"

8 Address bits

ex: SDIN = "01101001"

1 Idle bit

SDIN = “0”

1 Idle bit

SDIN = “0”

8 Read data bits

ex: SDO = "10011010"

8 Write data bits

ex: SDIN = "10010011"

SCLK

SCS

SDO

SDIN

Address[7], [6],... [0]

Data[7], [6],... [0]

Hi-Z Tri-state

SCLK

SCS

SDO

SDIN

Address[7], [6],... [0]

Data[7], [6],... [0]

Hi-Z Tri-state

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