CS9210 datasheet(11/39 Pages) NSC

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Signal Definitions (Continued)

LCASB#

(4 mA)

DRAM Bank B Low Byte Column Address Strobe

The column address strobe for the lower eight bits of data for Bank B

of the DRAM.

WEA#

(4 mA)

DRAM Bank A Write Enable

The write enable signal for Bank A of the DRAM.

WEB#

(4 mA)

DRAM Bank B Write Enable

The write enable signal for Bank B of the DRAM.

2.2.4

Memory Interface Signals (Continued)

Signal Name

Pin No.

Type

(Drive)

Description

2.2.5

Reset and Internal Test Pins

Signal Name

Pin No.

Type

(Drive)

Description

RESET#

132

Reset

This pin is the system reset input.

TEST

124

Reserved

This pin must be tied to ground. It is a National Semiconductor internal

test mode pin only.

2.2.6

Power and Ground Pins

Signal Name

Pin No.

Type

(Drive)

Description

VDD

1, 17, 36,

37, 55,

72, 73,

91, 108,

125, 144

PWR

Power Connection (total of 11 pins)

Power for the DRAM and system interface signals. These should be

supplied with 3.3V.

VSS

2, 18, 19,

38, 54,

71, 89,

90, 109,

126, 128

GND

Ground Connection (total of 11 pins)

Ground connection.

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