TDA8029HLSLASHC2 datasheet(35/58 Pages) PHILIPS

35 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

8.10.2.5

UART Status Register (USR)

The UART Status Register (USR) is used by the microcontroller to monitor the activity of the ISO UART and that of the

time-out counter. If any of the status bits FER, OVR, PE, EA, TO1, TO2 or TO3 are set, then signal INT0_N = LOW. The

bit having caused the interrupt is reset 2

µs after the rising edge of signal RD during a read operation of register USR.

If bit TBE/RBF is set and if the mask bit DISTBE/RBF within register UCR2 is not set, then also signal INT0_N = LOW.

Bit TBE/RBF is reset three clock cycles after data has been written in register UTR, or three clock cycles after data has

been read from register URR, or when changing from transmission mode to reception mode.

If LCT mode is used for transmitting the last character, then bit TBE is not set at the end of the transmission.

Table 52 UART status register, address Eh, read

Table 53 Description of register bits

BIT

543210

Symbol

TO3

TO2

TO1

OVR

FER

TBE/RBF

Reset value

00000

BIT

SYMBOL

DESCRIPTION

7TO3

Time-out counter 3. TO3 = 1 when counter 3 has reached its terminal count.

6TO2

Time-out counter 2. TO2 = 1 when counter 2 has reached its terminal count.

5TO1

Time-out counter 1. TO1 = 1 when counter 1 has reached its terminal count.

4EA

Early Answer. EA = 1 if the ﬁrst start-bit on the I/O pin during ATR has been detected

between the first 200 and nmax clock pulses with pin RST in LOW state (all activities on

the I/O during the first 200 clock pulses with pin RST LOW are not taken into account)

and before the first nmax clock pulses with pin RST in HIGH state. These two features are

re-initialized at each toggling of pin RST. nmax = 384 for TDA8029HL/C1; nmax = 368 for

TDA8029HL/C2.

3PE

Parity Error.

In protocol T = 0, bit PE = 1 if the UART has detected a number of received characters

with parity errors equal to the number written in bits PEC[2:0] or if a transmitted character

has been NAKed by the card a number of times equal to the value programmed in bits

PEC[2:0]. It is set at 10.5 ETU in the reception mode and at 11.5 ETU in the transmission

mode. A character received with a parity error is not stored in register FIFO in protocol

T = 0; the card should repeat this character.

In protocol T = 1, a character with a parity error is stored in the FIFO and the parity error

counter is not active.

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