CC1100-RTY1 datasheet(18/100 Pages) TI1

18 / 100 page

CC1100

SWRS038D

Page 18 of 92

Pin #

Pin Name

Pin type

Description

AVDD

Power (Analog)

1.8 -3.6 V analog power supply connection

RF_P

RF I/O

Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

RF_N

RF I/O

Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

AVDD

Power (Analog)

1.8 - 3.6 V analog power supply connection

AVDD

Power (Analog)

1.8 - 3.6 V analog power supply connection

GND

Ground (Analog)

Analog ground connection

RBIAS

Analog I/O

External bias resistor for reference current

DGUARD

Power (Digital)

Power supply connection for digital noise isolation

GND

Ground (Digital)

Ground connection for digital noise isolation

Digital Input

Serial configuration interface, data input

Table 13: Pinout Overview

Circuit Description

BIAS

RBIAS

XOSC_Q1

XOSC_Q2

CSn

SO (GDO1)

XOSC

SCLK

LNA

FREQ

SYNTH

ADC

RADIO CONTROL

RF_P

RF_N

GDO2

GDO0 (ATEST)

RC OSC

Figure 2:

CC1100 Simplified Block Diagram

A simplified block diagram of

CC1100 is shown

in Figure 2.

CC1100

features a low-IF receiver. The

received RF signal is amplified by the low-

noise amplifier (LNA) and down-converted in

quadrature (I and Q) to the intermediate

frequency (IF). At IF, the I/Q signals are

digitised by the ADCs. Automatic gain control

(AGC), fine channel filtering and demodulation

bit/packet

synchronization

are

performed

digitally.

The transmitter part of

CC1100 is based on

direct synthesis of the RF frequency. The

frequency synthesizer includes a completely

on-chip LC VCO and a 90 degree phase

shifter for generating the I and Q LO signals to

the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and

XOSC_Q2. The crystal oscillator generates the

reference frequency for the synthesizer, as

well as clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for

configuration and data buffer access.

The digital baseband includes support for

channel configuration, packet handling, and

data buffering.

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