DP83266 datasheet(69/152 Pages) NSC

69 / 152 page

70 Control Information (Continued)

Counter Overflow Mask Register (COMR)

The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR) If a bit in

Register COMR is set to One the corresponding bit in Register COLR will be applied to the Interrupt Condition Register which

can then be used to generate an interrupt to the CPU

All bits in this register are set to Zero upon reset

Access Rules

Address

Read

Write

01Dh

Always

RES

TKRCVD

FRTRX

FRNCOP

FRCOP

FRLST

FREI

FRRCV

Bit

Symbol

Description

RES

Reserved

TKRCVD

Token Received Counter Overflow Mask

This bit is used to mask COLRTKRCVD

FRTRX

Frame Transmitted Counter Overflow Mask

This bit is used to mask COLRFRTRX

FRNCOP

Frame Not Copied Counter Overflow Mask

This bit is used to mask COLRFRNCOP

FRCOP

Frame Copied Counter Overflow Mask

This bit is used to mask COLRFRCOP

FRLST

Lost Frame Counter Overflow Mask

This bit is used to mask COLRFRLST

FREI

Error Isolated Counter Overflow Mask

This bit is used to mask COLRFREI

FRRCV

Frame Received Counter Overflow Mask

This bit is used to mask COLRFRRCV

DP83266 데이터시트(PDF) 69 Page - National Semiconductor (TI)

DP83266 데이터시트(HTML) 69 Page - National Semiconductor (TI)

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