COP8CCR9IMT7SLASHNOPB datasheet(51/111 Pages) TI1

51 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

5.12.3.1.2 Exiting The High Speed Halt Mode

There is a choice of methods for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-

Input Wake-up.

5.12.3.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the

HALT mode and starts execution from address 0000H. The initialization software should determine what

special action is needed, if any, upon start-up of the device from HALT. The initialization of all registers

following a RESET exit from HALT is described in the Reset section of this manual.

5.12.3.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a transition received on one of the available Wake-

up pins. The pins used and the types of transitions sensed on the Multi-input pins are software

programmable. For information on programming and using the Multi-Input Wake-up feature, refer to the

Multi-Input Wake-up section.

A start-up delay is required between the device wake-up and the execution of program instructions,

depending on the type of chip clock. The start-up delay is mandatory, and is implemented whether or not

the CLKDLY bit is set. This is because all crystal oscillators and resonators require some time to reach a

stable frequency and full operating amplitude.

The IDLE Timer (Timer T0) provides a fixed delay from the time the clock is enabled to the time the

program execution begins. Upon exit from the HALT mode, the IDLE Timer is enabled with a starting

value of 256 and is decremented with each instruction cycle. (The instruction clock runs at one-fifth the

frequency of the high speed oscillator.) An internal Schmitt trigger connected to the on-chip CKI inverter

ensures that the IDLE Timer is clocked only when the oscillator has a large enough amplitude. (The

Schmitt trigger is not part of the oscillator closed loop.) When the IDLE Timer underflows, the clock signals

are enabled on the chip, allowing program execution to proceed. Thus, the delay is equal to 256

instruction cycles.

NOTE

To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the

instruction in the application program used for entering the HALT mode should be followed

by two consecutive NOP (no-operation) instructions.

5.12.3.1.5 Options

This device has two options associated with the HALT mode. The first option enables the HALT mode

feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option

will cause the microcontroller to ignore any attempts to HALT the device under software control. Note that

this device can still be placed in the HALT mode by stopping the clock input to the microcontroller, if the

program memory is masked ROM. See the Option section for more details on this option bit.

Functional Description

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB 데이터시트(PDF) 51 Page - Texas Instruments