DP83848JSQSLASHNOPB datasheet(14/84 Pages) TI1

14 / 84 page

Vcc

Hardware

RESET_N

MDC

32 clocks

Latch-In of Hardware

Configuration Pins

Dual Function Pins

Become Enabled As Outputs

input

output

T2.1.3

T2.1.2

T2.1.1

X1 clock

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

AC Timing Requirements (continued)

MIN

NOM

MAX

UNIT

ISOLATION TIMING (REFER TO Figure 5-26)

From software clear of bit 10 in the BMCR register

T2.26.1

100

µs

to the transition from Isolate to Normal Mode

From Deassertion of S/W or H/W Reset to

T2.26.2

500

µs

transition from Isolate to Normal mode

100 Mb/s X1 TO TX_CLK TIMING (REFER TO Figure 5-27)(26)

T2.27.1

X1 to TX_CLK delay

100 Mb/s Normal mode

(26) X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.

Figure 5-1. Power Up Timing

Specifications

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB 데이터시트(PDF) 14 Page - Texas Instruments

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