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DP83902AVLC 데이터시트(PDF) 41 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DP83902AVLC
상세설명  ST-NICTM Serial Network Interface Controller for Twisted Pair
PDF  70 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83902AVLC 데이터시트(HTML) 41 Page - National Semiconductor (TI)

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130 Bus Arbitration and Timing
The ST-NIC operates in three possible modes
 BUS MASTER (WHILE PERFORMING DMA)
 BUS SLAVE (WHILE BEING ACCESSED BY CPU)
 IDLE
TLF11157 – 21
Upon power-up the ST-NIC is in an indeterminate state Af-
ter receiving a hardware reset the ST-NIC is a bus slave in
the Reset State the receiver and transmitter are both dis-
abled in this state The reset state can be re-entered under
three conditions soft reset (Stop Command) hard reset
(RESET input) or an error that shuts down the receiver of
transmitter (FIFO underflow or overflow) After initialization
of registers the ST-NIC is issued a Start command and the
ST-NIC enters Idle state Until the DMA is required the
ST-NIC remains in idle state The idle state is exited by a
request from the FIFO on the case of receiver or transmit or
from the Remote DMA in the case of Remote DMA
operation After acquiring the bus in a BREQBACK hand-
shake the Remote or Local DMA transfer is completed and
the ST-NIC re-enters the idle state
DMA TRANSFERS TIMING
The DMA can be programmed for the following types of
transfers
16-Bit Address 8-bit Data Transfer
16-Bit Address 16-bit Data Transfer
32-Bit Address 8-bit Data Transfer
32-Bit Address 16-bit Data Transfer
All DMA transfers use BSCK for timing 16-Bit Address
modes require 4 BSCK cycles as shown below
16-Bit Address 8-Bit Data
TLF11157 – 22
41



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