DP83902AVLC datasheet(50/70 Pages) NSC

50 / 70 page

140 Preliminary Electrical Characteristics

Absolute Maximum Ratings

If MilitaryAerospace specified devices are required

please contact the National Semiconductor Sales

OfficeDistributors for availability and specifications

Supply Voltage (VCC)

05V to a70V

DC Input Voltage (VIN)

05V to VCC a 05V

DC Output Voltage (VOUT)

05V to VCC a 05V

Storage Temperature Range (TSTG)

65 Cto a150 C

Power Dissipation (PD)

800 mW

Lead Temp (TL) (Soldering 10 sec)

260 C

ESD Rating (RZAP e 15k CZAP e 100 pF)

15 kV

Pin to Pin

Pin to GND

Pin to VCC (g1 ZAP)

Clamp Diode Current

20 mA

Note

Absolute Maximum ratings are those values beyond

which the safety of the device cannot be guaranteed They

are not meant to imply that the device should be operated at

these limits

Note

All specifications in this datasheet are valid only if the

mandatory isolation is employed and all differential signals

are taken to exist at the AUI or TPI side of the isolation

Preliminary DC Specifications TA e 0 Cto70 C VCC e 5V g5% unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

VOH

Minimum High Level Output Voltage

IOH eb20 mAVCC b01

(Notes 1 4)

IOH eb20 mA

VOL

Minimum Low Level Output Voltage

IOL e 20 mA

(Notes 1 4)

IOL e 20 mA

VIH

Minimum High Level Input Voltage (Note 2)

VIH2

Minimum High Level Input Voltage

For RACK WACK (Note 2)

VIL

Maximum Low Level Input Voltage (Note 2)

VIL2

Maximum Low Level Input Voltage

For RACK WACK (Note 2)

VLOL

Good Link Output Voltage

IOL e 16 mA

IIN

Input Current

VI e VCC or GND

IINSEL

Input Current

VIN e VCC

2000

VIN e GND

IOZ

Minimum TRI-STATE

VOUT e VCC or GND

Output Leakage Current (Note 5)

ICC

Average Supply Current

X1 e 20 MHz Clock

(Note 3)

IOUT e 0 mA

140

VIN e VCC or GND

Note 1

These levels are tested dynamically using a limited amount of functional test patterns please refer to AC test load

Note 2

Limited functional test patterns are performed at these input levels The majority of functional tests are performed at levels of 0V and 3V

Note 3

This is measured with a 01 mF bypass capacitor between VCC and GND

Note 4

The low drive CMOS compatible VOH and VOL limits are not tested directly Detailed device characterization validates that this specification can be

guaranteed by testing the high drive TTL compatible VOL and VOH specification

Note 5

RA0–RA3 PRD WACK BREQ and INT pins are used as outputs in test mode and as a result are tested as if they are TRI-STATE inputoutputs For these

pins the input leakage specification is IOZ

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