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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83916 데이터시트(PDF) 84 Page - National Semiconductor (TI) |
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DP83916 데이터시트(HTML) 84 Page - National Semiconductor (TI) |
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84 / 96 page  70 AC and DC Specifications (Continued) BUS RETRY TLF11722 – 71 Number Parameter 20 MHz Units Min Max T41 Bus Retry Synchronous Setup Time to BSCK 5ns (Note 3) T41a Bus Retry Asynchronous 5ns Setup Time to BSCK (Note 3) T42 Bus Retry Hold Time from BSCK (Note 2) 7 ns T43 BSCK to HOLD High (Note 1) 25 ns T44 BSCK to HOLD Low (Note 1) 22 ns T47 BSCK to BR Low 25 ns T50 BSCK to BGACK High (Note 4) 30 ns Note 1 Depending upon the mode the SONIC-16 will assert and deassert HOLD from the rising or falling edge of BSCK Note 2 Unless Latched Bus Retry mode is set (LBR in the Data Configuration Register Section 432) BRT must remain asserted until after the Th state If Latched Bus Retry mode is used BRT does not need to satisfy T42 Note 3 T41 is for synchronous bus retry and T41a is for asynchronous bus retry (see Section 432 bit 15 Extended Bus Mode) Since T41a is an asynchronous setup time it is not necessary to meet it but doing so will guarantee that the bus exception occurs in the current memory transfer not the next Note 4 BGACK is driven high for approximately BSCK before going TRI-STATE 84 |
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