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DS99R101 데이터시트(PDF) 22 Page - Texas Instruments

부품명 DS99R101
상세설명  DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
PDF  29 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

DS99R101 데이터시트(HTML) 22 Page - Texas Instruments

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ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
RPWDNB
REN
RRFB
RESRVD
RIN+
RIN-
VDDOR2
VDDOR3
VDDR1
VDDR0
VDDPR1
VDDPR0
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
3.3V
DS99R102 (DES)
C3
C7
C4
C8
C9
C10
R1
C5
C1
VDDIR
VDDOR1
VSSPR0
VSSPR1
VSSR0
VSSR1
VSSIR
VSSOR1
VSSOR2
VSSOR3
LOCK
C2
C6
C1 to C4 = 0.01 P F
C5 to C8 = 0.1 P F
C9, C10 = 100 nF; 50WVDC, NPO or X7R
R1 = 100:
Serial
LVDS
Interface
LVCMOS
Parallel
Interface
GPO if used, or tie High (ON)
3.3V
3.3V
DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
www.ti.com
Figure 21. DS99R102 Typical Application Connection
TRUTH TABLES
DS99R101 Serializer Truth Table
TPWDNB
DEN
Tx PLL Status
LVDS Outputs
(Pin 9)
(Pin 18)
(Internal)
(Pins 19 and 20)
L
X
X
Hi Z
H
L
X
Hi Z
H
H
Not Locked
Hi Z
H
H
Locked
Serialized Data with Embedded Clock
DS99R102 Deserializer Truth Table
RPWDNB
REN
Rx PLL Status
ROUTn and RCLK
LOCK
(Pin 1)
(Pin 48)
(Internal)
(See Pin Diagram)
(Pin 17)
L
X
X
Hi Z
Hi Z
H
L
X
Hi Z
L = PLL Unocked;
H = PLL Locked
H
H
Not Locked
Hi Z
L
H
H
Locked
Data and RCLK Active
H
22
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R101 DS99R102



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