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DS99R101 데이터시트(PDF) 11 Page - Texas Instruments |
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DS99R101 데이터시트(HTML) 11 Page - Texas Instruments |
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11 / 29 page ![]() Ideal Sampling Position tBIT (1UI) Sampling Window Ideal Data Bit End Ideal Data Bit Beginning RxIN_TOL -L 2 tBIT ( ) RxIN_TOL -R Data Valid Before RCLK Data Valid After RCLK ROUT [7:0] Data Valid Before RCLK Data Valid After RCLK ROUT [15:8], LOCK Data Valid Before RCLK Data Valid After RCLK VDD/2 ROUT [23:16] RCLK tLOW tHIGH tROS tROH tROS tROH (group 1) (group 1) (group 2) (group 2) 1/2 UI 1/2 UI tROS tROH (group 3) (group 3) 1/2 UI 1/2 UI VDD/2 VDD/2 VDD/2 VDD/2 VDD/2 VDD/2 VDD/2 DS99R101, DS99R102 www.ti.com SNLS240D – MARCH 2007 – REVISED APRIL 2013 Figure 15. Deserializer Setup and Hold Times RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. Figure 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS99R101 DS99R102 |
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