PCM1798

SLES102 – DECEMBER 2003

www.ti.com

21

APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE

DATA

24

23

22

21

20

19

18

17

16

15

5

6

7

8

9

10

11

12

13

14

PCM1798

BCK

SCK

DGND

VDD

MUTE

FMT0

FMT1

ZERO

RST

AGND2

IOUTR–

VCC1

VCOML

VCOMR

IREF

IOUTR+

AGND3R

AGND1

MONO

1

2

3

4

CHSL

DEM

LRCK

28

27

26

25

VCC2L

AGND3L

IOUTL–

IOUTL+

VCC2R

DATA

Analog

Output Stage

(See Figure 23)

WDCK

BCK

SCK

External

Filter

Device

VDD

Figure 26. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application

Application for Interfacing With an External Digital Filter

For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter

to perform the interpolation function. The following pin settings enable the external digital filter application mode.

The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of

Figure 26. The word clock (WDCK) must be operated at 8

Pin Assignment When Using the External Digital Filter Interface