DP8459 datasheet(17/35 Pages) NSC

17 / 35 page

External Component Selection

Symbol

Parameter

Min

Typ

Max

Units

NOM

Charge Pump Nominal Operating

1.2

Ω

Current Setting Resistor ( Note 1 )

BOOST

Charge Pump Boost Current

1.2

∞

Ω

Setting Resistor ( Note 1 )

NOM

NOM Bypass Capacitor (Note 2 )

0.01

µF

BOOST

BOOST Bypass Capacitor (Note 2 )

0.01

µF

PUMP UP Open Emitter Output

510

Ω

Pull-Down Resistor

PUMP DOWN Open Emitter Output

510

Ω

Pull-Down Resistor

Note 1: The minimum allowed value for the parallel combination of RNOM and RBOOST is 1.2 kΩ.

Note 2: CNOM and CBOOST should be high quality, high frequency type.

3.0 PLL Applications: Loop Filter Design

In order to maintain greatest design ﬂexibility for the Customer,

all PLL ﬁlter components and Charge Pump gain setting

elements reside external to the DP8459. All PLL dynamics are

thus under the control of the system designer. The following is

a brief analysis of the DP8459 PLL; Section 3.1 contains a

derivation

component

values

based

projected

requirements within an example hard disk drive system.

Figure 16 represents the DP8459 PLL in simpliﬁed form.

Mathematical gain representations for each block are:

PG = 1/N

Pulse Gate equivalent gain

PC = 1/(2π)

Phase Comparator gain

CP = VCC/2Rp

Charge Pump gain where R

p = RNOM,

HGD high; R

p = RNOM||RBOOST, HGD low

VCO

= 1.2

VCO gain (

= operating center

frequency)

FIGURE 16. Basic DP8459 Phase Locked Loop Block Diagram

N is deﬁned as the number VCO cycles per recorded

ENCODED READ DATA pulse, or conversely, the ratio of the

VCO frequency to the ENCODED READ DATA frequency. The

aggregate block gain equation (excluding the loop ﬁlter) can be

written as:

B = 1.2 VCC fO/(2RpN)

The impedance of the loop ﬁlter is

The open loop system response G(s) is given by

This last equation reveals the PLL with this ﬁlter conﬁguration

is a third order system, which is typically difficult to analyze.

However, if C

2 << C1, it can be argued that the behavior of the

third order loop closely resembles that of a second order

system, allowing for a greatly simpliﬁed analysis.

If C

2 << C1, the impedance Z(s) approximates to

The overall open loop gain (including the ﬁlter) is then

Substituting K

B into the equation,

1 = RpC1 and τ2 = R1C1 are the pole and zero, respectively,

which govern the system response. The closed loop gain H(s)

TL/F/9322-18

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:06:00 ds009322 Rev. No. 1

Proof

DP8459 데이터시트(PDF) 17 Page - National Semiconductor (TI)

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