TMS320C31, TMS320LC31

DIGITAL SIGNAL PROCESSORS

SPRS035B – MARCH 1996 – REVISED JANUARY 1999

31

POST OFFICE BOX 1443

interrupt-acknowledge timing

The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and

goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.

The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 24

correspond with those in the NO. column of the table below.

timing parameters for IACK (see Note 7 and Figure 24)

NO.

’LC31-33

’C31-40

’LC31-40

’C31-50

’C31-60

’C31-80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

52

td(H1H-IACKL)

Delay time, H1 high to IACK

low

10

9

7

6

5

ns

53

td(H1H-IACKH)

Delay time, H1 high to IACK

high

10

9

7

6

5

ns

NOTE 7: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle

(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode

phase of the IACK instruction is extended.

H3

H1

IACK

ADDR

Data

52

53

Fetch IACK

Instruction

IACK Data

Read

Decode IACK

Instruction

Figure 24. Timing for IACK