PCF8575C

SCPS123F – MARCH 2005 – REVISED JANUARY 2015

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11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the PCF8575C device, common PCB layout practices should be

followed but additional concerns related to high-speed data transfer such as matched impedances and

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors

the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors should be placed as close to the PCF8575C as possible. These best practices are shown in

Figure 24.

For the layout example provided in Figure 24, it would be possible to fabricate a PCB with only 2 layers by using

a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to

route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other

internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are

connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace

needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 24.

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