LP3950SLSLASHNOPB datasheet(5/38 Pages) TI1

5 / 38 page

LP3950

www.ti.com

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

Thermal Properties

Junction-to-Ambient Thermal Resistance

72°C/W

(

θJA), NPC0032A Package

(1)

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

Electrical Characteristics

(1) (2)

Limits in standard typeface are for TJ = +25°C. Limits in boldface type apply over the operating ambient temperature range

(

−40°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to Figure 2 with: VDD1 = VDD2 = VDDA = 2.8V, CVDD1 =

CVDD2 = CVDDA = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz

(3).

Symbol

Parameter

Condition

Min

Typ

Max

Units

IVDD

Standby Supply Current

NSTBY = L (register)

µA

(VDD1 + VDD2 + VDDA current)

SCK, SS, SI, NRST = H

No-Load Supply Current

NSTBY = H (reg.)

300

400

µA

(VDD1 + VDD2 + VDDA current, boost off)

EN_BOOST = L (reg.)

SCK, SS, SI, NRST = H

Full Load Supply Current

NSTBY = H (reg.)

850

µA

(VDD1 + VDD2 + VDDA current, boost on)

(4)

EN_BOOST = H (reg.)

SCK, SS, SI, NRST = H

All Outputs Active

IVDDIO

VDDIO Supply Current

1.0 MHz SCK Frequency

µA

CL = 50 pF at SO Pin

IVDDA

Audio Circuitry Supply Current(5)

INPUT_SEL = [10] (register)

550

µA

VREF

Reference Voltage(6)

IREF ≤ 1.0 nA Only for Test Purpose

1.230

(1)

All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).

(2)

Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the

most likely norm.

(3)

Low-ESR Surface-Mount Ceramic Capacitors are used in setting electrical characteristics.

(4)

Audio block inactive.

(5)

In single-ended and in differential mode one audio buffer only is active and IVDDA will be reduced by 90 µA (typ).

(6)

VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.

Submit Documentation Feedback

Product Folder Links: LP3950

LP3950SL/NOPB 데이터시트(PDF) 5 Page - Texas Instruments

LP3950SL/NOPB 데이터시트(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

데이터시트 다운로드

링크 URL