SS

SCK

SI

SO

Don't Care

A6

A5

A4

A3

A2

A1

A0

R/W

0

D7

D6

D5

D4

D3

D2

D1

D0

SS

SCK

SI

SO

A6

A5

A4

A3

A2

A1

A0

1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

LP3950

www.ti.com

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

Control Interface

The LP3950 supports three different interface modes:

1. SPI interface (4 wire, serial)

3. Direct enable (2 wire, enable lines)

User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both

interface modes. Note that the pin configurations will be based on the status of the IF_SEL pin.

IF_SEL

Interface

Pin Configuration

Comment

HIGH

SPI

SCK

(clock)

SI

(data in)

SO

(data out)

SS

(chip select)

LOW

SCL

(clock)

Use pull up resistor for SCL.

SDA

(data in/out)

Use pull up resistor for SDA.

SI

SI HIGH

→ address is 51'h;

SO

(NC)

SI LOW

→ address is 50'h;

Unused pin SO can be left unconnected.

SPI Interface

The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one

read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO

output is normally in high-impedance state and it is active only during when data is sent out during a read cycle.

A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current

consumption in the circuitry.

The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be

low during the cycle transmission. SS resets the interface when high and it has to be taken high between

successive cycles. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the

falling edge of SCK.

Figure 3. SPI Write Cycle

Figure 4. SPI Read Cycle

Copyright © 2004–2013, Texas Instruments Incorporated

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