Top View

D+

ID

D-

VBUS

VBUS

VBAT

GND

U2

U1

AUD1

AUD2

DP

DN

DSS

MIC

SDA

SCL

INT\

RES

GND

CAP

A

B

C

D

E

1

2

3

4

5

GND

GND

VBAT

EXPDET

LP8727

www.ti.com

SNVS898A – OCTOBER 2012 – REVISED MAY 2013

Connection Diagram

Figure 1. 25-Bump (0.4mm Pitch) DSBGA Package

PIN NAME

PIN #

TYPE

DESCRIPTION

AUD1

B1

AI

Stereo Audio input (Left).

AUD2

C1

AI

Stereo Audio input (Right).

CAP

D2

A

Internal LDO output. Connect a 1.0 µF ceramic capacitor to GND.

D-

E3

DI/O

Common data I/O. Connect to D- on Mini / Micro USB connector.

D+

E2

DI/O

Common data I/O. Connect to D+ on Mini / Micro USB connector.

DN

A2

DI/O

USB differential data I/O (-).

DP

A3

DI/O

USB differential data I/O (+).

Default switch status input. Internally pulled down with a 300 k

Ω resistor.

DSS

D3

A

Logic high for UART startup and logic low for USB startup.

Overvoltage protected LDO output for low-voltage USB system. Connect a 1.0

EXPDET

B5

P

µF ceramic capacitor to GND.

GND

C2, C3, C4, D4

G

Ground.

ID

E1

DI

USB ID Input. Connect to ID on Mini / Micro USB connector.

Open-drain output for interrupt, active low. Typ. 10 k

Ω pull-up resistor is

INT\

B2

DO

required.

MIC

A1

AO

Microphone output.

Bias output for ID detection and Microphone. Connect a 2.2 k

Ω resistor to ID

RES

D1

A

pin.

SCL

B4

DI

Serial interface clock input. Connect a 1.5 k

Ω pullup resistor.

SDA

B3

DI/O

Serial interface data input/output. Connect a 1.5 k

Ω pullup resistor.

U1

A5

DI/O

UART data Rx / USB differential data I/O (-).

U2

A4

DI/O

UART data Tx / USB differential data I/O (+).

Main battery connection.

VBAT

C5, D5

P

Requires 10 µF ceramic capacitor when a battery is not connected.

VBUS

E4, E5

P

USB VBUS input.

(1)

A: Analog Pin, D: Digital Pin, I: Input Pin, DI/O Digital Input/Output Pin, G: Ground, O: Output Pin, I/O: Input/Output Pin, P: Power

Connection

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